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PD - 94530B
ARM28XXT SERIES HYBRID - HIGH RELIABILITY 1 MEGA-RAD HARDENED DC/DC CONVERTER
Description
The ARM Series of three output DC/DC converters are designed specifically for use in the high-dose radiation environments encountered during deep space planetary missions. The extremely high level of radiation tolerance inherent in the ARM design is assured as a result of extensive research, thorough analysis and testing, careful selection of components and lot verification testing of finished hybrids. Many of the best circuit design features characterizing earlier International Rectifier products have been incorporated into the ARM topology. Capable of uniformly high performance through long term exposures in radiation intense environments, this series sets the standard for distributed power systems demanding high performance and reliability. The ARM converters are hermetically sealed in a rugged, low profile package utilizing copper core pins to minimize resistive DC losses. Long-term hermeticity is assured through use of parallel seam welded lid attachment along with International Rectifier's rugged ceramic pin-to-package seal. Axial lead orientation facilitates preferred bulkhead mounting to the principal heat-dissipating surface. Manufactured in a facility fully qualified to MIL-PRF38534, these converters are fabricated utilizing DSCC qualified processes. For available screening options refer to device screening table in the data sheet. Variations in electrical, mechanical and screening specifications may be accommodated. Contact IR Santa Clara for special requirements.
28V Input, Triple Output
ARM Features
n n n n n n n n n n n n n n n Total Dose > 1MRad (Si) SEE Hardened to LET up to 83 Mev.cm2/mg Derated per MIL-STD-975 & MIL-STD-1547 Output Power Range 3 to 30 Watts 19 to 50 Volt Input Range Input Undervoltage Lockout High Electrical Efficiency > 80% Full Performance from -55C to +125C Continuous Short Circuit Protection 12.8 W / in3 Output Power Density True Hermetic Package External Inhibit Port Externally Synchronizable Fault Tolerant Design 5V, 12V or 5V, 15V Outputs Available
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08/11/06
ARM28XXT Series Specifications
Absolute Maximum Ratings
Input Voltage range -0.5V to +80VDC
Recommended Operating Conditions
Input Voltage range +19V to +60VDC +19V to +50V for full derating to MIL-STD-975 3.0W to 30W -55C to +125C -55C to +85C for full derating to MIL-STD-975
5% Maximum rated Minimum Output Current Output Power current, any Output Soldering temperature 300C for 10 seconds Operating case temperature Storage case temperature -65C to +135C
Electrical Performance -55C < TCASE < +125C, VIN=28V, CL=0 unless otherwise specified.
Parameter Output voltage accuracy Symbol VOUT IOUT = 250mAdc, TC = +25C ARM2812(dual) IOUT = 250mAdc, TC = +25C ARM2815(dual) Output power Note 5 Output current Note 5 POUT IOUT 19 Vdc< VIN < 50Vdc (main) 19 Vdc< VIN < 50Vdc (dual) Line regulation Note 3 VRLINE 150 mAdc < IOUT < 3000 mAdc 19 Vdc< VIN < 50Vdc 75 mAdc < IOUT < 750 mAdc 150 mAdc < IOUT < 3000 mAdc 19 Vdc< VIN < 50Vdc 75 mAdc < IOUT < 750 mAdc 19 Vdc< VIN < 50Vdc (dual) Total regulation VR All conditions of Line, Load, (main) Cross Regulation, Aging, Temperature and Radiation ARM2812(dual) ARM2815(dual) IOUT = minimum rated, Pin 3 open Input current Output ripple voltage Note 6 Input ripple current Note 6 Switching frequency Efficiency IIN Pin 3 shorted to pin 2 (disabled) VRIP IRIP FS Eff 19 Vdc< VIN < 50Vdc IOUT = 3000 mAdc (main), 500 mAdc (dual) 19 Vdc< VIN < 50Vdc IOUT = 3000 mAdc (main), 500 mAdc (dual) Sychronization input open. (pin 6) IOUT = 3000 mAdc (main), 500 mAdc (dual) 225 80 8.0 100 150 275 mVp.p mAp.p KHz % -500 4.8 11.1 13.9 +500 5.2 V 12.9 16.0 250 mA (main) (dual) (main) (dual) (main) Cross regulation Note 8 VRCROSS 75 -15 -60 -180 -300 -10 750 +15 mV +60 +180 mV +300 +10 mV 11.50 14.50 3.0 150 12.50 15.15 30 3000 mAdc W Conditions IOUT = 1.5Adc, TC = +25C (main) Min 4.95 Max 5.05 Vdc Units
Load regulation Note 4
VRLOAD
For Notes to Specifications, refer to page 3
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ARM28XXT Series
Electrical Performance (Continued)
Parameter Enable Input open circuit voltage drive current (sink) voltage range Synchronization Input frequency range pulse high level pulse low level pulse rise time pulse duty cycle Power dissipation, load fault Output response to step load changes Notes 7, 11 Recovery time from step load changes Notes 11, 12 Output response to step line changes Notes 10, 11 Recovery time from step line changes Notes 10, 11,13 PD VTLD 50% Load to/from 100% load 10% Load to/from 50% load TTLD 50% Load to/from 100% load VTLN IOUT = 3000 mAdc VIN = 19 V to/from 50 V IOUT = 500 mAdc IOUT = 3000 mAdc VIN = 19 V to/from 50 V IOUT = 500 mAdc IOUT = minimum and full rated (dual) Turn on delay Note 14 Capacitive load Notes 9, 10 Isolation TDLY CL ISO IOUT = minimum and full rated (main) No effect on DC performance (dual) 500VDC Input to Output or any pin to case (except pin 12) 100 100 M 5.0 1500 20 500 F ms (main) (dual) (main) (dual) (main) Turn on overshoot VOS -350 -1050 200 350 mVPK 1050 500 500 500 mV s -200 200 200 s Symbol Conditions 19 Vdc< VIN < 50Vdc Min 3.0 0.1 -0.5 225 4.5 -0.5 40 20 Short circuit, any output 10% Load to/from 50% load -200 Max 5.0 50.0 310 10.0 0.25 80 7.5 200 mVPK Units V mA V KHz V V V/s % W
External clock signal on Sync. input (pin 4)
TTLN
Notes to Specifications Table
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. Operation outside absolute maximum/minimum limits may cause permanent damage to the device. Extended operation at the limits may permanently degrade performance and affect reliability. Device performance specified in Electrical Performance table is guaranteed when operated within recommended limits. Operation outside recommended limits is not specified. Parameter measured from 28V to 19 V or to 50V while loads remain fixed. Parameter measured from nominal to minimum or maximum load conditions while line remains fixed. Up to 750 mA is available from the dual outputs provided the total output power does not exceed 30W. Guaranteed for a bandwidth of DC to 20MHz. Tested using a 20KHz to 2MHz bandwidth. Load current is stepped for output under test while other outputs are fixed at half rated load. Load current is fixed for output under test while other output loads are varied for any combination of minimum to maximum. A capacitive load of any value from 0 to the specified maximum is permitted without comprise to DC performance. A capacitive load in excess of the maximum limit may interfere with the proper operation of the converter's short circuit protection, causing erratic behavior during turn on. Parameter is tested as part of design characterization or after design or process changes. Thereafter, parameters shall be guaranteed to the limits specified in the table. Load transient rate of change, di/dt 2A/s. 2 A/Sec. Recovery time is measured from the initiation of the transient to where VOUT has returned to within 1% of its steady state value. Line transient rate of change, dv/dt 50V/s. 50 V/Sec. Turn on delay time is for either a step application of input power or a logical low to high transition on the enable pin (pin 3) while power is present at the input.
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ARM28XXT Series
Group A Tests VIN= 28Volts, CL =0 unless otherwise specified.
Test Output voltage accuracy Symbol VOUT IOUT = 250mAdc IOUT = 250mAdc Output power Note 1 Output current Note 1 Output regulation Note 4 POUT IOUT VIN = 19 V, 28V, 50 V (main) VIN 19 V, 28V, 50 V (dual) VR IOUT = 150, 1500, 3000mAdc VIN = 19 V, 28V, 50 V IOUT = 75, 310, 625mAdc IOUT = 75, 250, 500mAdc (main) 2812(dual) 2815(dual) 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 4, 5, 6 1 2, 3 1, 2, 3 4, 5, 6 4, 5, 6 4, 5, 6 4, 5, 6 (main) Turn on overshoot Turn on delay Note 7 Isolation VOS TDLY ISO IOUT = minimum and full rated (dual) IOUT = minimum and full rated 500VDC Input to output or any pin to case (except pin 12) 4, 5, 6 4, 5, 6 1 5.0 100 1500 20 ms M 4, 5, 6 -200 -200 225 80 78 7.5 200 mVPK 50% Load to/from 100% load Recovery time from step load changes Notes 5, 6 10% Load to/from 50% load TTL 50% Load to/from 100% load 200 500 mV 200 200 s 75 4.8 11.1 14.0 500 5.2 V 12.9 15.8 250 mA Pin 3 shorted to pin 2 (disabled) Output ripple Note 2 Input ripple Note 2 Switching frequency Efficiency Power dissipation, load fault Output response to step load changes Notes 3, 5 VRIP IRIP FS Eff PD VIN = 19 V, 28V, 50 V IOUT = 3000mA main, 500mA dual VIN = 19 V, 28V, 50 V IOUT = 3000mA main, 500mA dual Synchronization pin (pin 6) open IOUT = 800mA main, 500mA dual Short circuit, any output 10% Load to/from 50% load VTL 8.0 100 150 275 mVP-P mAP-P KHz % W ARM2812(dual) ARM2815(dual) 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 11.70 14.50 3.0 150 12.30 15.15 30 3000 mA W Conditions unless otherwise specified IOUT = 1.5 Adc (main) Group A Subgroups 1, 2, 3 Min 4.95 Max 5.05 V Units
IOUT = minimum rated, Pin 3 open Input current IIN
Notes to Group A Test Table
1. 2. 3. 4. 5. 6. 7. Parameter verified during dynamic load regulation tests Guaranteed for DC to 20 MHz bandwidth. Test conducted using a 20KHz to 2MHz bandwidth. Load current is stepped for output under test while other outputs are fixed at half rated load. Each output is measured for all combinations of line and load. Only the minimum and maximum readings for each output are recorded. Load step transition time 10S. Recovery time is measured from the initiation of the transient to where VOUT has returned to within 1% of its steady state value. Turn on delay time is tested by application of a logical low to high transition on the enable pin (pin 3) with power present at the input.
8. Subgroups 1 and 4 are performed at +25C, subgroups 2 and 5 at -55C and subgroups 3 and 6 at +125C.
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ARM28XXT Series
Radiation Performance
The radiation tolerance characteristics inherent in the ARM28XXT converter are based on the results of the ground-up design effort on the ART2800T program and started with specific radiation design goals. By imposing sufficiently large margins on those electrical parameters subject to the degrading effects of radiation, appropriate elements were selected for incorporation into the ART2800T circuit. Known radiation data was utilized for input to PSPICE and RadSPICE in the generation of circuit performance verification analyses. Thus, electrical performance capability under all environmental conditions including radiation was well understood before first application of power to the inputs. The principal ART2800T design goal was a converter topology, which because of large design margins, had radiation performance essentially independent of wafer-lot radiation performance variations. Radiation tests on random ART2800T manufacturing lots provide continued confirmation of the soundness of the design goals as well as justification for the element selection criteria. To achieve the radiation levels specified for the ARM28XXT, the ART2800T topology is utilized as the basis but lot assurance testing is utilized as part of the screening process to assure the specified level. Each ARM28XXT converter is delivered with lot test data at the hybrid level supporting the minimum TID specification. Other radiation specifications are assured by design and generic data are available on request. The following table specifies guaranteed minimum radiation exposure levels tolerated while maintaining specification limits.
Radiation Specification Tcase = 25C
Test Total Ionizing Dose Conditions MIL-STD-883, Method 1019.4 Operating bias applied during exposure MIL-STD-883, Method 1021 1E8 1E11 MIL-STD-883, Method 1017.2 3E12 Rads (Si)/sec Neutron /cm MeV* cm/mg Min 1,000 Unit KRads (Si)
Dose Rate Temporary Saturation Survival Neutron Fluence
Heavy Ions (Single event effects)
BNL Tandem Van de Graaff Generator
83
International Rectifier currently does not have a DSCC certified Radiation Hardness Assurance Program.
Standard Quality Conformance Inspections on ARM28XXT Series (Flight Screened)
Inspection Group A Group B Group C Application Part of Screening on Each Unit Each Inspection Lot First Inspection Lot or Following Class 1 Change In Line (Part of Element Evaluation) Samples 100% * 5 units 10 units
Group D
3 units
* Group B quantity for Option 2 End of Line
QCI. No Group B samples reuired for Option 1, In-line.
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ARM28XXT Series
Figure I. Block Diagram
1
+Input Under-Voltage Detector
EMI Filter
11
+15 Vout Dual
10
Output Return
9 3
Primary Bias & Reference Short Circuit
-15 Vout Dual +5 Vdc Output Output Return
13
Enable
14
4
Sync In
Pulse Width Modulator
Sample Hold
Input Return
2
Circuit Description and Application Information Operating Guidelines
The ARM28XXT series of converters have been designed using a single ended forward switched mode converter topology. (refer to Figure I.) Single ended topologies enjoy some advantage in radiation hardened designs in that they eliminate the possibility of simultaneous turn on of both switching elements during a radiation induced upset; in addition, single ended topologies are not subject to transformer saturation problems often associated with double ended implementations. The design incorporates an LC input filter to attenuate input ripple current. A low overhead linear bias regulator is used to provide bias voltage for the converter primary control logic and a stable, well regulated reference for the error amplifier. Output control is realized using a wide band discrete pulse width modulator control circuit incorporating a unique non-linear ramp generator circuit. This circuit helps stabilize loop gain over variations in line voltage for superior output transient response. Nominal conversion frequency has been selected as 250 KHz to maximize efficiency and minimize magnetic element size. Output voltages are sensed using a coupled inductor and a patented magnetic feedback circuit. This circuit is relatively insensitive to variations in temperature, aging, radiation and manufacturing tolerances making it particularly well suited to radiation hardened designs. The control logic has been designed to use only radiation tolerant components, and all current paths are limited with series resistance to limit photo currents. Other key circuit design features include short circuit protection, undervoltage lockout and an external synchronization port permitting operation at an externally set clock rate. The circuit topology used for regulating output voltages in the ARM28XXT series of converters was selected for a number of reasons. Significant among these is the ability to simultaneously provide adequate regulation to three output voltages while maintaining modest circuit complexity. These attributes were fundamental in retaining the high reliability and insensitivity to radiation that characterizes device performance. Use of this topology dictates that the user maintain the minimum load specified in the electrical tables on each output. Attempts to operate the converter without a load on any output will result in peak charging to an output voltage well above the specified voltage regulation limits, potentially in excess of ratings, and should be avoided. Output loads that are less than specification minimums will result in regulation performance outside the limits presented in the tables. In most practical applications, this lower bound on the load range does not present a serious constraint; however the user should be mindfull of the results. Characteristic curves illustrating typical regulation performance are shown in Figures VII, VIII and IX.
Thermal Considerations
The ARM series of converters is capable of providing relatively high output power from a package of modest volume. The power density exhibited by these devices is obtained by combining high circuit efficiency with effective methods of heat removal from the die junctions. Good design practices have effectively addressed this requirement inside the device. However when operating at maximum loads, significant heat generated at the die junctions must be carried away by conduction from the base. To maintain case temperature at or below the specified maximum of 125C, this heat can be transferred by attachment to an appropriate heat dissipater held in intimate contact with the converter base-plate.
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ARM28XXT Series
Effectiveness of this heat transfer is dependent on the intimacy of the baseplate-heatsink interface. It is therefore suggested that a heat transferring medium possessing good thermal conductivity is inserted between the baseplate and heatsink. A material utilized at the factory during testing and burn-in processes is sold under the (R) trade name of Sil-Pad 4001. This particular product is an insulator but electrically conductive versions are also available. Use of these materials assures optimum surface contact with the heat dissipater by compensating for minor surface variations. While other available types of heat conducting materials and thermal compounds provide similar effectiveness, these alternatives are often less convenient and are frequently messy to use. A conservative aid to estimating the total heat sink surface area (A HEAT SINK) required to set the maximum case temperature rise (T) above ambient temperature is given by the following expression:
-1. 43
Thus, a total heat sink surface area (including fins, if any) of approximately 32 in2 in this example, would limit case rise to 35C above ambient. A flat aluminum plate, 0.25" thick and of approximate dimension 4" by 4" (16 in 2 per side) would suffice for this application in a still air environment. Note that to meet the criteria, both sides of the plate require unrestricted exposure to the ambient air.
Inhibiting Converter Output
As an alternative to application and removal of the DC voltage to the input, the user can control the converter output by providing an input referenced, TTL compatible, logic signal to the enable pin 3. This port is internally pulled "high" so that when not used, an open connection on the pin permits normal converter operation. When inhibited outputs are desired, a logical "low" on this port will shut the converter down. An open collector device capable of sinking at least 100 A connected to enable pin 3 will work well in this application. A benefit of utilization of the enable input is that following initial charge of the input capacitor, subsequent turn-on commands will induce no uncontrolled current inrush.
T A HEAT SINK 0.85 80 P
where
- 5.94
Figure II. Enable Input Equivalent Circuit
Vin
T = Case temperature rise above ambient 1 P = Device dissipation in Watts = P - 1 Eff
OUT
5K
2N2907A
As an example, assume that it is desired to maintain the case temperature of an ARM2815T at +65C or less while operating in an open area whose ambient temperature does not exceed +35C; then T = 65 - 35 = 35C From the Specification Table, the worst case full load efficiency for this device is 80%; therefore the maximum power dissipation at full load is given by
64K Enable Input 186K 150K 150K Input Return 2N2222A 5.6 V 150K 2N2222A
Converter inhibit is initiated when this transistor is turned off
1 . P = 30 * - 1 = 30 * (0.25) = 75W .80
and the required heat sink area is
35 A HEAT SINK = 0.85 80 * 7.5
-1. 43
- 5.94 = 318 in 2 .
1Sil-Pad is a registered Trade Mark of Bergquist, Minneapolis, MN
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ARM28XXT Series
Synchronization
When using multiple converters, system requirements may dictate operating several converters at a common system frequency. To accommodate this requirement, the ARM28XXT type converter provides a synchronization input port (pin 4). Circuit topology is as illustrated in Figure III. The sync input port permits synchronization of an ARM converter to any compatible external frequency source operating in the band of 225 to 310 KHz. The synchronization input is edge triggered with synchronization initiated on the negative transition. This input signal should be a negative going pulse referenced to the input return and have a 20% to 80% duty cycle. Compatibility requires the negative transition time to be less than 100 ns with a minimum pulse amplitude of +4.25 volts referred to the input return. In the event of failure of an external synchronization source, the converter will revert to its own internally set frequency. When external synchronization is not desired, the sync in port may be left open (unconnected) permitting the converter to operate at its' own internally set frequency.
Parallel Operation
Although no special provision for forced current sharing has been incorporated in the ARM28XXT series, multiple units may be operated in parallel for increased output power applications. The 5 volt outputs will typically share to within approximately 10% of their full load capability and the dual (15 volt) outputs will typically share to within 50% of their full load. Load sharing is a function of the individual impedance of each output and the converter with the highest nominal set voltage will furnish the predominant load current.
Input Undervoltage Protection
A minimum voltage is required at the input of the converter to initiate operation. This voltage is set to a nominal value of 16.8 volts. To preclude the possibility of noise or other variations at the input falsely initiating and halting converter operation, a hysteresis of approximately 1.0 volts is incorporated in this circuit. The converter is guaranteed to operate at 19 Volts input under all specified conditions.
Input Filter
To attenuate input ripple current, the ARM28XXT series converters incorporate a single stage LC input filter. The elements of this filter comprise the dominant input load impedance characteristic, and therefore determine the nature of the current inrush at turn-on. The input filter circuit elements are as shown in Figure IV.
Figure III. Synchronization Input Equivalent Circuit
+10V
5K
Figure IV. Input Filter Circuit
Sync Input 47pf 2N2907A
10
5K Input Return
+ Input 3.6 H
5.4 fd
Output Short Circuit Protection
Protection against accidental short circuits on any output is provided in the ARM28XXT converters. This protection is implemented by sensing primary switching current and, when an over-current condition is detected, switching action is terminated and a restart cycle is initiated. If the short circuit condition has not been cleared by the time the restart cycle has completed, another restart cycle is initiated. The sequence will repeat until the short circuit condition is cleared at which time the converter will resume normal operation. The effect is that during a shorted condition, a series of narrow pulses are generated at approximately 5% duty cycle which periodically sample the state of the load. Thus device power dissipation is greatly reduced during this mode of operation.
Input Return
8
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ARM28XXT Series
Additional Filtering
Although internal filtering is provided at both the input and output terminals of the ARM2800 series, additional filtering may be desirable in some applications to accommodate more stringent system requirements. While the internal input filter of Figure IV keeps input ripple current below 100 mAp-p, an external filter is available that will further attenuate this ripple content to a level below the CE03 limits imposed by MIL-STD-461B. Figure V is a general diagram of the Advanced Analog ARF461 filter module designed to operate in conjunction with the ARM2800 series converters to provide that attenuation. It is important to be aware that when filtering high frequency noise, parasitic circuit elements can easily dominate filter performance. Therefore, it is incumbent onthe designer to exercise care when preparing a circuit layout for such devices. Wire runs and lengths should be minimized, high frequency loops should be avoided and careful attention paid to the construction details of magnetic circuit elements. Tight magnetic coupling will improve overall magnetic performance and reduce stray magnetic fields.
Figure VI. External Output Filter
+5 V C1 C6 C2 5V Return L2 C3 C7 L4 +5V Return +15V Out L1 L3 +5V Out
Figure V. ARF461 Input EMI Filter
+15V
15V Return
15V Return C4 C8 C5
This circuit as shown in Figure V is constructed using the same quality materials and processes as those employed in the ARM2800 series converters and is intended for use in the same environments. This filter is fabricated in a complementary package style whose output pin configuration allows pin to pin connection between the filter and the converter. More complete information on this filter can be obtained from the ARF461 data sheet. An external filter may also be added to the output where circuit requirements dictate extremely low output ripple noise. The output filter described by Figure VI has been characterized with the ARM2815T using the values shown in the associated material list.
-15V
-15V Out
G G! G" G# 8%
A&AA6XB! AivsvyhAAHhtADpAprAQIAE# "$U8AArvhyr A&AA6XB!#AvsvyhAAHhtADpAprAQIAE# "$U8AArvhyr A#AA6XB! AAHhtADpAprAQIAHQQ$$#'AArvhyr A$AA6XB! AivsvyhAAHhtADpAprAQIAHQQ$$#'AArvhyr A &AA $WAH"(%!!$ #AUhhy
8 8$ A!!AArA8FSAprhvpAphhpv 8&8' A!$AA$WAH"(%!!$%'AUhhy
Measurement techniques can impose a significant influence on results. All noise measurements should be measured with test leads as close to the device output pins and as short as physically possible. Probe ground leads should be kept to a minimum length.
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ARM28XXT Series
Performance Characteristics (Typical @ 25C)
Figure VII. Efficiency vs Output Power for Three Line Voltages.
85 80
Efficiency (%)
75 70 65 60 55 50 0 5 10 15 20 25 30 35
18V 28V 50V
Output Power (Watts)
Figure VIII.
5 V Output Regulation Limits Including all conditions of Line, Load and Cross Regulation.
5.2 Output Voltage 5.1 5.0 4.9 4.8 4.7 0.0 0.5 1.0 1.5 Output Current (Amps) 2.0 2.5 3.0
Upper Limit Lower Limit
10
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ARM28XXT Series
Performance Characteristics (Typical @ 25C) (Continued)
Figure IX.
15 V Regulation Curves
For Three conditions of Load on the 5 Volt Output.
17.0 Output Voltage (Magnitude) 5V Load = 3.0A 5V Load = 1.5A 5V Load = 150 mA
16.0
15.0
14.0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 Output Current (Each Output)
Figure X.
Cross Regulation Curves 5 Volt Output as a function of 15 Volt Load Current for Three 5 Volt Loads.
5.2 5.1
Output Voltage
5.0 4.9 4.8 4.7 4.6 4.5 0 0.1 0.2 0.3 0.4 0.5 0.6 5V Load = 150mA 5V Load = 1.5A 5V Load = 3.0A
15 Volt Load Current
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ARM28XXT Series
Mechanical Outline
O 0.136 - 6 Holes
0.040 Pin Dia.
5
8 9 10 11 12 13 14
1.675
2.200
6 x 0.200 = 1.200
1.950
0.375 0.263 0.138 0.300 0.150 1.400 2.400 2.700 0.275 0.240
Mounting Plane
0.500 Max
3.25 Ref. Max 0.050 Flange
Note:
1. Dimensions are in inches. 2. Base Plate Mounting Plane Flatness 0.003 maximum. 3. Unless otherwise specified, tolerances are = 2 .XX = .01 .XXX = .005
.XXX = .005 4. Device Weight - 120 grams maximum. 5. Materials: Case: Cold rolled steel Cover: Kovar Pins: Copper cored Alloy 42 with ceramic insulators
Pin Designation
Pin # 1 2 3 4 5 8 9 10 11 12 13 14 Designation + Input Input Return Enable Sync In NC NC -15Vdc Output 15Vdc Output return +15Vdc Output Chassis +5Vdc Output +5Vdc Output return
12
1
2
3
4
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ARM28XXT Series
Device Screening
Requirement
Temperature Range Element Evaluation Non-Destructive Bond Pull Internal Visual Temperature Cycle Constant Acceleration PIND Burn-In Final Electrical ( Group A ) PDA Seal, Fine and Gross Radiographic External Visual MIL-PRF-38534 2023 2017 1010 2001, Y1 Axis 2020 1015 MIL-PRF-38534 & Specification MIL-PRF-38534 1014 2012 2009
MIL-STD-883 Method
No Suffix
d
CK
d
EM
-55C to +85C N/A N/A
-55C to +85C Class K Yes Yes Cond C 3000 Gs Cond A 320 hrs @ 125C ( 2 x 160 hrs ) -55C, +25C, +85C 2% Cond A, C Yes Yes
-55C to +85C Class K Yes Yes Cond C 3000 Gs Cond A 320 hrs @ 125C ( 2 x 160 hrs ) -55C, +25C, +85C 2% Cond A, C Yes Yes
c
Cond C 3000 Gs N/A 48 hrs @ 125C
-55C, +25C, +85C N/A Cond A N/A
c
Notes:
c d
Best commercial practice. CK is DSCC class K compliant without radiation performance. No Suffix is a radiation rated device but not available as a DSCC qualified SMD per MIL-PRF-38534.
International Rectifier currently does not have a DSCC certified Radiation Hardness Assurance Program.
Part Numbering ARM 28 15 T /EM
Model Input Voltage
28 = 28V
Screening Level
(Please refer to Screening Table)
No Suffix, CK, EM
Output
Output Voltage
15 = 5V, 15V 12 = 5V, 12V
T = Triple
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 252-7105 IR SANTA CLARA: 2270 Martin Av., Santa Clara, California 95050, Tel: (408) 727-0500 Visit us at www.irf.com for sales contact information. Data and specifications subject to change without notice. 08/2006
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